ds058 (v1.2) june 25, 2001 www.xilinx.com 1 preliminary product specification 1-800-255-7778 ? 2000 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? 5 ns pin-to-pin logic delays system frequency up to 178 mhz 36 macrocells with 800 usable gates available in small footprint packages - 44-pin plcc (34 user i/o pins) - 44-pin vqfp (34 user i/o pins) - 48-pin csp (36 user i/o pins) - 64-pin vqfp (36 user i/o pins) optimized for high-performance 3.3v systems - low power operation - 5v tolerant i/o pins accept 5 v, 3.3v, and 2.5v signals - 3.3v or 2.5v output capability - advanced 0.35 micron feature size cmos fastflash? technology advanced system features - in-system programmable - superior pin-locking and routability with fastconnect ii? switch matrix - extra wide 54-input function blocks - up to 90 product-terms per macrocell with individual product-term allocation - local clock inversion with three global and one product-term clocks - individual output enable per output pin - input hysteresis on all user and boundary-scan pin inputs - bus-hold circuitry on all user pin inputs - full ieee standard 1149.1 boundary-scan (jtag) fast concurrent programming slew rate control on individual outputs enhanced data security features excellent quality and reliability - endurance exceeding 10,000 program/erase cycles - 20 year data retention - esd protection exceeding 2,000v pin-compatible with 5v-core xc9536 device in the 44-pin plcc package and the 48-pin csp package description the xc9536xl is a 3.3v cpld targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems. it is comprised of two 54v18 function blocks, providing 800 usable gates with propagation delays of 5 ns. see figure 2 for architecture overview. power estimation power dissipation in cplds can vary substantially depend- ing on the system frequency, design application and output loading. to help reduce power dissipation, each macrocell in a xc9500xl device may be configured for low-power mode (from the default high-performance mode). in addi- tion, unused product-terms and macrocells are automati- cally deactivated by the software to further conserve power. for a general estimate of i cc , the following equation may be used: i cc (ma) = mc hp (0.5) + mc lp (0.3) + mc(0.0045 ma/mhz) f where: mc hp = macrocells in high-performance (default) mode mc lp = macrocells in low-power mode mc = total number of macrocells used f = clock frequency (mhz) this calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each function block with no output loading. the actual i cc value varies with the design application and should be verified during normal system operation. figure 1 shows the above estimation in a graphical form. 0 xc9536xl high performance cpld ds058 (v1.2) june 25, 2001 05 preliminary product specification r figure 1: typical i cc vs. frequency for xc9536xl clock frequency (mhz) typical i cc (ma) 0 100 200 250 ds058_01_061101 60 20 178 mhz 125 mhz 30 150 50 10 40 50 h i gh p erfo r m a nc e l ow powe r
xc9536xl high performance cpld 2 www.xilinx.com ds058 (v1.2) june 25, 2001 1-800-255-7778 preliminary product specification r figure 2: xc9536xl architecture function block outputs (indicated by the bold line) drive the i/o blocks directly. in-system programming controller jtag controller i/o blocks function block 1 macrocells 1 to 18 macrocells 1 to 18 jtag port 3 54 i/o/gts i/o/gsr i/o/gck i/o i/o i/o i/o 2 1 i/o i/o i/o i/o 3 ds058_02_081500 1 function block 2 54 18 18 fastconnect ii switch matrix
xc9536xl high performance cpld ds058 (v1.2) june 25, 2001 www.xilinx.com 3 preliminary product specification 1-800-255-7778 r absolute maximum ratings recommended operation conditions quality and reliability characteristics dc characteristic over recommended operating conditions symbol description value units v cc supply voltage relative to gnd ? 0.5 to 4.0 v v in input voltage relative to gnd (1) ? 0.5 to 5.5 v v ts voltage applied to 3-state output (1) ? 0.5 to 5.5 v t stg storage temperature (ambient) ? 65 to +150 o c t sol maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 o c t j junction temperature +150 o c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to ? 2.0 v or overshoot to +7.0v, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. 2. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol parameter min max units v ccint supply voltage for internal logic and input buffers commercial t a = 0 o c to 70 o c3.0 3.6 v industrial t a = ? 40 o c to +85 o c3.0 3.6 v v ccio supply voltage for output drivers for 3.3v operation 3.0 3.6 v supply voltage for output drivers for 2.5v operation 2.3 2.7 v v il low-level input voltage 0 0.80 v v ih high-level input voltage 2.0 5.5 v v o output voltage 0 v ccio v symbol parameter min max units t dr data retention 20 - years n pe program/erase cycles (endurance) 10,000 - cycles v esd electrostatic discharge (esd) 2,000 - volts symbol parameter test conditions min max units v oh output high voltage for 3.3v outputs i oh = ? 4.0 ma 2.4 v output high voltage for 2.5v outputs i oh = ? 500 a90% v ccio v v ol output low voltage for 3.3v outputs i ol = 8.0 ma - 0.4 v output low voltage for 2.5v outputs i ol = 500 a-0.4v i il input leakage current v cc = max v in = gnd or v cc -10 a i ih i/o high-z leakage current v cc = max v in = gnd or v cc -10 a c in i/o capacitance v in = gnd f = 1.0 mhz -10pf i cc operating supply current (low power mode, active) v i = gnd, no load f = 1.0 mhz 10 (typical) ma
xc9536xl high performance cpld 4 www.xilinx.com ds058 (v1.2) june 25, 2001 1-800-255-7778 preliminary product specification r ac characteristics symbol parameter xc9536xl-5 xc9536xl-7 xc9536xl-10 units minmaxminmaxminmax t pd i/o to output valid - 5.0 - 7.5 - 10.0 ns t su i/o setup time before gck 3.7 - 4.8 - 6.5 - ns t h i/o hold time after gck 0 - 0 - 0 - ns t co gck to output valid - 3.5 - 4.5 - 5.8 ns f system multiple fb internal operating frequency - 178.6 - 125 - 100 mhz t psu i/o setup time before p-term clock input 1.7 - 1.6 - 2.1 - ns t ph i/o hold time after p-term clock input 2.0 - 3.2 - 4.4 - ns t pco p-term clock output valid - 5.5 - 7.7 - 10.2 ns t oe gts to output valid - 4.0 - 5.0 - 7.0 ns t od gts to output disable - 4.0 - 5.0 - 7.0 ns t poe product term oe to output enabled - 7.0 - 9.5 - 11.0 ns t pod product term oe to output disabled - 7.0 - 9.5 - 11.0 ns t ao gsr to output valid - 10.0 - 12.0 - 14.5 ns t pao p-term s/r to output valid - 10.5 - 12.6 - 15.3 ns t wlh gck pulse width (high or low) 2.8 - 4.0 - 4.5 - ns t plh p-term clock pulse width (high or low) 5.0 - 6.5 - 7.0 - ns figure 3: ac load circuit device output output type v test 3.3v 2.5v v test r 1 320 ? 250 ? r 1 r 2 c l r 2 360 ? 660 ? c l 35 pf 35 pf ds058_03_081500 v ccio 3.3v 2.5v
xc9536xl high performance cpld ds058 (v1.2) june 25, 2001 www.xilinx.com 5 preliminary product specification 1-800-255-7778 r internal timing parameters symbol parameter xc9536xl-5 xc9536xl-7 xc9536xl-10 units min max min max min max buffer delays t in input buffer delay - 1.5 - 2.3 - 3.5 ns t gck gck buffer delay - 1.1 - 1.5 - 1.8 ns t gsr gsr buffer delay - 2.0 - 3.1 - 4.5 ns t gts gts buffer delay - 4.0 - 5.0 - 7.0 ns t out output buffer delay - 2.0 - 2.5 - 3.0 ns t en output buffer enable/disable delay - 0 - 0 - 0 ns product term control delays t ptck product term clock delay - 1.6 - 2.4 - 2.7 ns t ptsr product term set/reset delay - 1.0 - 1.4 - 1.8 ns t ptts product term 3-state delay - 5.5 - 7.2 - 7.5 ns internal register and combinatorial delays t pdi combinatorial logic propagation delay - 0.5 - 1.3 - 1.7 ns t sui register setup time 2.3 - 2.6 - 3.0 - ns t hi register hold time 1.4 - 2.2 - 3.5 - ns t ecsu register clock enable setup time 2.3 - 2.6 - 3.0 - ns t echo register clock enable hold time 1.4 - 2.2 - 3.5 - ns t coi register clock to output valid time - 0.4 - 0.5 - 1.0 ns t aoi register async. s/r to output delay - 6.0 - 6.4 - 7.0 ns t rai register async. s/r recover before clock 5.0 7.5 10.0 ns t logi internal logic delay - 1.0 - 1.4 - 1.8 ns t logilp internal low power logic delay - 5.0 - 6.4 - 7.3 ns feedback delays t f fastconnect ii feedback delay - 1.9 - 3.5 - 4.2 ns time adders t pta incremental product term allocator delay - 0.7 - 0.8 - 1.0 ns t slew slew-rate limited delay - 3.0 - 4.0 - 4.5 ns
xc9536xl high performance cpld 6 www.xilinx.com ds058 (v1.2) june 25, 2001 1-800-255-7778 preliminary product specification r xc9536xl i/o pins xc9536xl global, jtag and power pins function block macro- cell pc44 vq44 cs48 vq64 bscan order function block macro- cell pc44 vq44 cs48 vq64 bscan order 1 1 2 40 d6 9 105 2 1 1 39 d7 8 51 1 2 3 41 c7 10 102 2 2 44 38 e5 7 48 135 (1) 43 (1) b7 (1) 15 (1) 99 2 3 42 (1) 36 (1) e6 (1) 5 (1) 45 1 4 442c61196 2 4 4337e76 42 156 (1) 44 (1) b6 (1) 16 (1) 93 2 5 40 (1) 34 (1) f6 (1) 2 (1) 39 1 6 8 2 a6 19 90 2 6 39 (1) 33 (1) g7 (1) 64 (1) 36 177 (1) 1 (1) a7 (1) 17 (1) 87 2 7 38 32 g6 63 33 1 8 9 3 c5 20 84 2 8 37 31 f5 62 30 19115b52281 2 93630g56127 1 10 12 6 a4 24 78 2 10 35 29 f4 60 24 1 11 13 7 b4 25 75 2 11 34 28 g4 57 21 1 12 14 8 a3 27 72 2 12 33 27 e3 56 18 1 13 18 12 b2 33 69 2 13 29 23 f2 50 15 1 14 19 13 b1 35 66 2 14 28 22 g1 48 12 1 15 20 14 c2 36 63 2 15 27 21 f1 45 9 1 16 22 16 c3 38 60 2 16 26 20 e2 44 6 1 17 24 18 d2 42 57 2 17 25 19 e1 43 3 1 18 - - d3 39 54 2 18 - - e4 49 0 notes: 1. global control pin. pin type pc44 vq44 cs48 vq64 i/o/gck1 5 43 b7 15 i/o/gck2 6 44 b6 16 i/o/gck3 7 1 a7 17 i/o/gts1 42 36 e6 5 i/o/gts2 40 34 f6 2 i/o/gsr 39 33 g7 64 tck 17 11 a1 30 tdi 15 9 b3 28 tdo 30 24 g2 53 tms 16 10 a2 29 v ccint 3.3v 21, 41 15, 35 c1, f7 3, 37 v ccio 2.5v/3.3v 32 26 g3 55 gnd 10, 23, 31 4, 17, 25 a5, d1, f3 21, 41, 54 no connects - - c4, d4 1, 4, 12, 13, 14, 18, 23, 26, 31, 32, 34, 40, 46, 47, 51, 52, 58, 59
xc9536xl high performance cpld ds058 (v1.2) june 25, 2001 www.xilinx.com 7 preliminary product specification 1-800-255-7778 r ordering information component availability revision history the following table shows the revision history for this document. xc9536xl -5 pc 44 c example: temperature range number of pins package type device type speed grade device ordering options speed package temperature -10 10 ns pin-to-pin delay pc44 44-pin plastic lead chip carrier (plcc) c = commercial t a = 0 c to +70 c -7 7.5 ns pin-to-pin delay vq44 44-pin quad flat pack (vqfp) i = industrial t a = ? 40 c to +85 c -5 5 ns pin-to-pin delay cs48 48-pin chip scale package -4 4 ns pin-to-pin delay vq64 64-pin quad flat pack (vqfp) pins 44 44 48 64 type plastic plcc plastic vqfp plastic csp plastic vqfp code pc44 vq44 cs48 vq64 xc9536xl -10 c, i c, i c, i c, i -7 c, i c, i c, i c, i -5c ccc notes: 1. c = commercial (t a = 0 o c to +70 o c); i = industrial (t a = ? 40 o c to +85 o c). date version revision 09/28/98 1.0 initial xilinx release. 08/28/00 1.1 added vq44 package. 06/25/01 1.2 removed -4 device. added c4 and d4 pins to cs48 no connects in pinout table. added industrial availability to -7 device.
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